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CY2277A
Pentium(R)/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel 82430TX and 2 DIMMs or 3 SO-DIMMs
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution to meet requirements of Pentium(R), Pentium(R) II, 6x86, or K6 motherboards -- Four CPU clocks at 2.5V or 3.3V -- Up to eight 3.3V SDRAM clocks -- Seven 3.3V synchronous PCI clocks, one free running -- Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable by serial interface -- One 2.5V IOAPIC clock at 14.318 MHz -- Two 3.3V Ref. clocks at 14.318 MHz * Factory-EPROM programmable CPU, PCI, and USB/IO clock frequencies for custom configuration * Factory-EPROM programmable output drive and slew rate for EMI customization * MODE Enable pin for CPU_STOP and PCI_STOP * I2CTM serial configuration interface * Available in space-saving 48-pin SSOP and TSSOP packages. and IO clock frequencies are factory-EPROM programmable for easy customization with fast turnaround times. The CY2277A has power-down, CPU stop and PCI stop pins for power management control. The CPU stop and PCI stop are controlled by the MODE pin. They are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven LOW. Additionally, these inputs are synchronized on-chip, enabling glitch-free transitions. When the CPU_STOP input is asserted, the CPU outputs are driven LOW. When the PCI_STOP input is asserted, the PCI outputs (except the free-running PCI clock) are driven LOW. Finally, when the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2277A outputs are designed for low EMI emission. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2277A Selector Guide
Clock Outputs CPU (60, 66.6MHz) CPU (33.3, 66.6MHz) CPU (I2C selectable) PCI (CPU/2) SDRAM USB/IO (48 or 24MHz) IOAPIC (14.318 MHz) Ref (14.318MHz) CPU-PCI delay
Note: 1. One free-running PCI clock.
-1/-1M 4 --7[1] 6/8 2 1 2 1-6 ns
-2 --4 7[1] 6/8 2 1 2 1-6 ns
-3 -4 -7[1] 6/8 2 1 2 1-6 ns
-12 4 --7[1] 6/8 2 1 2 1-4 ns
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pentium II, 6X86, and K6 portable PCs designed with the Intel(R) 82430TX or similar chipsets. There are three available options as shown in the selector guide The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up to nine selectable frequencies. There are up to eight 3.3V SDRAM clocks and seven PCI clocks, running at one half the CPU clock frequency. One of the PCI clocks is free-running. Additionally, the part outputs two 3.3V USB/IO clocks at 48 MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and two 3.3V reference clocks at 14.318 MHz. The CPU, PCI, USB,
Logic Block Diagram
IOAPIC (14.318 MHz) VDDQ2 XTALIN
XTALOUT
14.318 MHz OSC. CPU PLL STOP LOGIC
Pin Configuration
SSOP Top View REF [0-1] (14.318) CPUCLK[0-3] VDDCPU
REF1 REF0 VSS XTALIN XTALOUT MODE VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS SEL SDATA SCLK VDDQ3 USBCLK/IOCLK USBCLK/IOCLK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AVDD PWR_SEL VDDQ2 IOAPIC PWR_DWN VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP AVDD
SEL MODE
EPROM
SDRAM[0-5] SDRAM6/CPU_STOP
SYS PLL
SDRAM7/PCI_STOP
/2 Delay STOP LOGIC SERIAL INTERFACE CONTROL LOGIC Divide and Mux Logic
PWR_DWN SCLK SDATA
PCI[0-5] PCICLK_F USBCLK/IOCLK[0:1]
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
CY2277A-1,-1M,-2,-3,-12
*
408-943-2600 October 12, 1998
CY2277A
Pin Summary
Name VDDQ3 VDDQ2 VDDCPU AVDD VSS XTALIN[2] XTALOUT MODE SEL SDATA SCLK PWR_DWN PWR_SEL SDRAM7/PCI_STOP SDRAM6/CPU_STOP SDRAM[0:5] CPUCLK[0:3] PCICLK[0:5] PCICLK_F IOAPIC REF[0:1] USBCLK/IOCLK
[2]
Pins 7, 15, 21, 28, 34 46 40 25, 48 4 5 6 18 19 20 44 47 26 27 36, 35, 33, 32, 30, 29 42, 41, 39, 38 9, 11, 12, 13, 14, 16 8 45 1, 2 22, 23
Description 3.3V Digital voltage supply IOAPIC Digital voltage supply, 2.5V CPU Digital voltage supply, 2.5V or 3.3V 3.3V Analog voltage supply Reference crystal input Reference crystal feedback Mode select input, enables power management features Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function tables.) I2C serial data input for serial configuration port I2C serial clock input for serial configuration port Active low control input to put osc., PLLs, and outputs in power down state Power select input, indicates whether VDDCPU is at 2.5V or 3.3V HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD) SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled when MODE is LOW SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled when MODE is LOW SDRAM clock outputs, have same frequency as CPU clocks CPU clock outputs PCI clock outputs PCI clock output, free-running IOAPIC clock output Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load USB or IO clock outputs, frequency selected by serial word
3, 10, 17, 24, 31, 37, 43 Ground
Note: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
CY2277A
Function Table (-1, -1M, -12)
SEL 0 1 XTALIN 14.318 MHz 14.318 MHz CPUCLK[0:3] SDRAM[0:7] 60.0 MHz 66.67 MHz PCICLK[0:5] PCICLK_F 30.0 MHz 33.33 MHz REF[0:1] IOAPIC 14.318 MHz 14.318 MHz USBCLK / IOCLK[3] 48.0 MHz / 24.0 MHz 48.0 MHz / 24.0 MHz
Function Table (-3)
SEL 0 1 XTALIN 14.318 MHz 14.318 MHz CPUCLK[0:3] SDRAM[0:7] 33.33 MHz 66.67 MHz PCICLK[0:5] PCICLK_F 16.67 MHz 33.33 MHz REF[0:1] IOAPIC 14.318 MHz 14.318 MHz USBCLK / IOCLK[3] 48.0 MHz / 24.0 MHz 48.0 MHz / 24.0 MHz
Function Table (-2)[4, 5]
Pin 18 SEL[6] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 I2C Control - Byte 0[7] Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU Freq (Target) 66.8 75.0 60.0 55.0 68.4 50.0 83.3 33.3 68.4 50.0 83.3 33.3 66.8 75.0 60.0 55.0 Outputs (MHz) PCI Freq (CPU/2) 33.4 37.5 30.0 27.5 34.2 25.0 41.65 16.67 34.2 25.0 41.65 16.67 33.4 37.5 30.0 27.5 CPU Freq (Actual) 66.818 75.000 60.000 55.012 68.409 49.947 83.306 33.298 68.409 49.947 83.306 33.298 66.818 75.000 60.000 55.012 PPM 272 0 0 217 133 1057 69 1107 133 1057 69 1107 272 0 0 217
Actual Clock Frequency Values (-1, -1M, -3, -12)
Clock Output CPUCLK, SDRAM CPUCLK, SDRAM USBCLK[8] IOCLK Target Frequency (MHz) 66.67 60.0 48.0 24.0 Actual Frequency (MHz) 66.654 60.0 48.008 24.004 PPM -195 0 167 167
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V
Notes: 3. On power-up, the default frequency on these outputs is 48 MHz. 4. All AC specs for duty cycle, skew, jitter, and rise/fall time remain the same. 5. The above frequencies support Intel Pentium and Pentium II, AMD K6, and Cyrix processors. 6. SEL = 0 OR SEL = 1 gives all the same CPU frequencies on the outputs. In this case, the CPU and PCI frequencies are I2C controllable. Therefore, the user can have jumperless frequency changes. 7. The above I2C bits will NOT affect the other clocks in the system. 8. Meets Intel USB clock requirements.
3
CY2277A
Power Management Logic
CPU_STOP X 0 0 1 1 PCI_STOP X 0 1 0 1 PWR_DWN 0 1 1 1 1 CPUCLK Low Low Low 66/60 MHz 66/60 MHz PCICLK Low Low 33/30 MHz Low 33/30 MHz PCICLK_F Stopped Running Running Running Running Other Clocks Stopped Running Running Running Running Osc. Off Running Running Running Running PLLs Off Running Running Running Running
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2277A is:
Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable)
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' on -1, -1M, -3, -12 Freq. Sel. Bit on -2 (Reserved) drive to `0' on -1, -1M, -3, -12 Freq. Sel. Bit on -2 (Reserved) drive to `0' on -1, -1M, -3, -12 Freq. Sel. Bit on -2 48/24 MHz (Frequency Select) 1 = 48 MHz (default), 0 = 24 MHz 48/24 MHz (Frequency Select) 1 = 48 MHz (default), 0 = 24 MHz Bit 1 1 1 0 0 Bit 0 1 - Three-State (see table below) 0 - N/A 1 - Test Mode (see table below) 0 - Normal Operation Bit 7 -Bit 6 -Bit 6 -Bit 5 -Bit 5 -Bit 4 -Bit 4 -Bit 3 23 Bit 2 22 Bit 1 -Bit 0
A6 1
A5 1
A4 0
A3 1
A2 0
A1 0
A0 1
R/W ----
Select Functions
Outputs Functional Description Three-State Test Mode CPU Hi-Z TCLK/2[9] PCI, PCI_F Hi-Z TCLK/4 SDRAM Hi-Z TCLK/2 Ref Hi-Z TCLK IOAPIC Hi-Z TCLK IOCLK Hi-Z TCLK/4 USBCLK Hi-Z TCLK/2
Note: 9. TCLK supplied on the XTALIN, PIN 4.
4
CY2277A
Byte 1: CPU, 24/48 MHz Active/Inactive Register(1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 23 22 -N/A 38 39 41 42 Description 48/24 MHz (Active/Inactive) 48/24 MHz (Active/Inactive) (Reserved) drive to `0' Not Used, drive 0 CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register(1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -8 16 14 13 12 11 9 Pin # Description (Reserved) drive to `0' PCICLK_F (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 26 Bit 6 27 Bit 5 29 Bit 4 30 Bit 3 32 Bit 2 33 Bit 1 35 Bit 0 36
Byte 4: SDRAM Active/Inactive Register(1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A N/A N/A N/A N/A Description Not used, drive to `0' Not used, drive to `0' Not used, drive to `0' Not used, drive to `0' Not used, drive to `0' Not used, drive to `0' Not used, drive to `0' Not used, drive to `0'
Byte 5: Peripheral Active/Inactive Register(1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # ---45 --1 2 Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' IOAPIC (Active/Inactive) (Reserved) drive to `0' (Reserved) drive to `0' REF1 (Active/Inactive) REF0 (Active/Inactive)
Byte 6: Reserved, for future use
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing).... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
5
CY2277A
Operating Conditions[10]
Parameter AVDD, V DDQ3 VDDCPU Description Analog and Digital Supply Voltage 2.5V CPU Supply Voltage (-1, -1M, -2, -3) 2.5V CPU Supply Voltage (-12) 3.3V CPU Supply Voltage 2.5V IOAPIC Supply Voltage (-1, -1M, -2, -3) 2.5V IOAPIC Supply Voltage (-12) 3.3V IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, USBCLK/IOCLK, REF1, IOAPIC PCICLK, SDRAM REF0 Reference Frequency, Oscillator Nominal Value Min. 3.135 2.375 2.375 3.135 2.375 2.375 3.135 0 10 30, 20 20 14.318 Max. 3.465 2.9 2.625 3.465 2.9 2.625 3.465 70 20 30 45 14.318 Unit V V
VDDQ2
V
TA CL
C pF
f(REF)
MHz
Electrical Characteristics (-1, -2, -3, -12)
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage High-level Output Voltage
[11]
Test Conditions Except Crystal Inputs Except Crystal Inputs I2C inputs only VDDQ2 = VDDCPU = 2.375V IOH = 18 mA CPUCLK IOH = 18 mA IOAPIC IOL = 29 mA CPUCLK IOL = 29 mA IOAPIC IOH = 32 mA CPUCLK IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOH = 26 mA IOCLK IOH = 36 mA REF0 IOH = 26 mA REF1
Min. Max. Unit 2.0 0.8 0.7 2.0 0.4 2.4 V V V V V V
Low-level Output Voltage[11] VDDQ2 = VDDCPU = 2.375V High-level Output Voltage[11] VDDQ3, AVDD, VDDCPU = 3.135V
VOL
Low-level Output Voltage[11] VDDQ3, AVDD, VDDCPU = 3.135V
IOL = 24 mA CPUCLK IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOL = 21 mA IOCLK IOL = 29 mA REF0 IOL = 21 mA REF1
0.4V
V
IIH IIL IIL IOZ IDD IDD IDDS
Input High Current Input Low Current Input Low Current Output Leakage Current
VIH = V DD VIL = 0V, except PWR_SEL VIL = 0V, PWR_SEL only Three-state
-10
+10 10 100
A A A A mA mA A
-10
+10 250 120 150
Power Supply Current[11, 12] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz Power Supply Current[11, 12] VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs Power-down Current Current draw in power-down state, PWR_SEL = VDD
Notes: 10. Electrical parameters are guaranteed with these operating conditions. 11. Guaranteed by design and characterization. Not 100% tested in production. 12. Power supply current will vary with number of outputs which are running.
6
CY2277A
Electrical Characteristics (-1M)
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs I2C inputs only IOH = 12.6 mA CPUCLK IOH = 16.7mA Low-level Output Voltage[11] VDDQ2 = VDDCPU = 2.375V High-level Output Voltage[11] VDDQ3, AVDD, VDDCPU = 3.135V IOAPIC 0.4 2.4 V V IOL = 18.2 mA CPUCLK IOL = 23.1 mA IOAPIC IOH = 32.2 mA SDRAM IOH = 32.2 mA PCICLK IOH = 32.2 mA USBCLK IOH = 32.2 mA IOCLK IOH = 32.2 mA REF0 IOH = 32.2 mA REF1 VOL Low-level Output Voltage[11] VDDQ3, AVDD, VDDCPU = 3.135V IOL = 23.8 mA SDRAM IOL = 23.8 mA PCICLK IOL = 23.8 mA USBCLK IOL = 23.8 mA IOCLK IOL = 23.8 mA REF0 IOL = 23.8 mA REF1 IIH IIL IIL IOZ IDD IDD IDDS Input High Current Input Low Current Input Low Current Output Leakage Current VIH = V DD VIL = 0V, except PWR_SEL VIL = 0V, PWR_SEL only Three-state -10 -10 +10 10 100 +10 250 120 150 A A A A mA mA A 0.4V V 2.0 Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V
High-level Output Voltage[11] VDDQ2 = VDDCPU = 2.375V
Power Supply Current[11, 12] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz Power Supply Current[11, 12] VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs Power-down Current Current draw in power-down state, PWR_SEL = VDD
7
CY2277A
Switching Characteristics (-1, -3) [11, 13, 15]
Parameter t1 Output CPUCLK SDRAM USBCLK IOCLK REF [0,1] IOAPIC PCI CPUCLK, IOAPIC PCI USBCLK, IOCLK, REF0 SDRAM REF1 CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK SDRAM PCICLK USBCLK, IOCLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle[14] Test Conditions t1 = t1A / t1B Min. 45 Typ. 50 Max. 55 Unit %
t1 t2
Output Duty Cycle[14] CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, I/O, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-1, -3) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
t1 = t1A / t1B Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.66 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V
40 0.75 0.75 0.75 0.8
50
55 4.0 4.0 4.0 4.0
% V/ns
t2 t2
V/ns V/ns
t2 t2 t3 t3 t4 t4 t5 t6 t7 t8 t8 t8 t8 t9
Between 0.4V and 2.4V SDRAM clocks at 66.66 MHz Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency
1.0 0.5 0.4 0.5
4.0 2.0 2.13 2.0 2.5
V/ns V/ns ns ns ns ns ps ns ps ps ps ps ns ms
0.4 0.5
2.13 2.0 2.5 100 400 6.0 775 450 650 500 1.3 3
1.0
2.0
t10
Frequency Slew Rate
2
MHz/ ms
Notes: 13. All parameters specified with loaded outputs. 14. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V. 15. Over the operating range unless otherwise specified.
8
CY2277A
Switching Characteristics (-1M) [11, 13, 15]
Parameter t1 Output CPUCLK SDRAM USBCLK REF [0,1] IOAPIC PCI CPUCLK, IOAPIC PCI USBCLK, REF0 SDRAM REF1 CPUCLK USBCLK CPUCLK USBCLK CPUCLK PCICLK SDRAM CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK SDRAM PCICLK USBCLK, IOCLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle
[14]
Test Conditions t1 = t1A / t1B
Min. 45
Typ. 50
Max. 55
Unit %
t1 t2
Output Duty Cycle[14] CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate CPU Clock Rise Time USB Clock Rise Time CPU Clock Fall Time USB Clock Fall Time CPU-CPU Clock Skew PCI-PCI Clock Skew SDRAM-SDRAM Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
t1 = t1A / t1B Between 0.4V and 2.0V, VDDCPU = 2.5V CPU clocks at 66.66 MHz Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V Between 0.4V and 2.4V SDRAM clocks at 66.66 MHz Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.0V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.0V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V Measured at 1.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks Measured at 1.5V Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency
45 0.60
50
55 4.0
% V/ns
t2 t2 t2 t2 t3 t3 t4 t4 t5 t5 t5 t6 t7 t8 t8 t8 t8 t9
0.65 0.65 0.70 0.5 0.4 0.4 100
4.0 4.0 4.0 2.0 2.4 2.5 2.4 2.5 250 400 300
V/ns V/ns V/ns V/ns ns ns ns ns ps ps ps ns ps ps ps ps ps ms
1.0
2.0
6.0 600 525 600 400 900 3
t10
Frequency Slew Rate
2
MHz/ ms
9
CY2277A
Switching Characteristics (-2) [11, 13, 15]
Parameter t1 Output CPUCLK SDRAM USBCLK IOCLK REF [0,1] IOAPIC PCI CPUCLK, IOAPIC PCI USBCLK, IOCLK, REF0 SDRAM REF1 CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK SDRAM PCICLK USBCLK, IOCLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle
[14]
Test Conditions t1 = t1A / t1B
Min. 40
Typ. 50
Max. 55
Unit %
t2
CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, I/O, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1 Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-2) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.8 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V
0.75 0.75 0.7 0.8
4.0 4.0 4.0 4.0
V/ns
t2 t2
V/ns V/ns
t2 t2 t3 t3 t4 t4 t5 t6 t7 t8 t8 t8 t9
Between 0.4V and 2.4V SDRAM clocks at 66.8 MHz Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency
1.0 0.5 0.4 0.5
4.0 2.0 2.13 2.0 2.5
V/ns V/ns ns ns ns ns ps ns ns ps ps ns ms
0.4 0.5
2.13 2.0 2.5 100 400 6.0 1.3 650 600 1.3 3
1.0
2.0
t10
Frequency Slew Rate
2
MHz/ ms
10
CY2277A
Switching Characteristics (-12) [11, 13, 15, 16]
Parameter t1 t2 Output All Clocks CPUCLK, IOAPIC PCI REF0 SDRAM REF1 USBCLK IOCLK CPUCLK USBCLK, IOCLK CPUCLK USBCLK, IOCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK PCICLK CPUCLK, PCICLK, SDRAM CPU, PCI, SDRAM Description Output Duty Cycle
[14]
Test Conditions t1 = t1A / t1B Between 0.6V and 1.8V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V CPU clocks at 66.6 MHz Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.8V and 2.4V, VDDCPU = 3.3V Between 0.5V and 2.0V SDRAM clocks at 66.6 MHz Between 0.4V and 2.4V
Min. 45 1.0 1.0 1.0 1.0 1.5 0.5
Typ. 50
Max. 55 4.0 4.0 4.0 4.0 4.0 2.0
Unit % V/ns
CPU and IOAPIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF1, USB and IO Rising and Falling Edge Rate CPU Clock Rise Time USB Clock and I/O Clock Rise Time CPU Clock Fall Time USB Clock and I/O Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew (-12) CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
t2 t2 t2 t2
V/ns V/ns V/ns V/ns
t3 t3 t4 t4 t5 t6 t7 t8 t8 t9
Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Between 2.4V and 0.4V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up Rate of change of frequency
0.4 0.4 1.0 0.4 0.4 1.0 100 1.0
2.0 2.0 4.0 2.0 2.0 4.0 250 4.0 500 250 500 3
ns ns ns ns ps ns ps ps ps ms
t10
Frequency Slew Rate
2
MHz/ ms
Note: 16. Parameters specified with: VDDCPU=2.5V, VDDQ2=2.5V, VDDQ3=3.3V.
11
CY2277A
Timing Requirement for the I2C Bus
Parameter t10 t11 t12 t13 t14 t15 t16 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The LOW period of the clock. The HIGH period of the clock. Setup time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters. for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns s ns s Max. 100 Unit kHz s s s s s s
t17 t18 t19 t20
Switching Waveforms
Duty Cycle Timing
t1B
t1A
CPUCLK Outputs HIGH/LOW Time
t1C VDD OUTPUT 0V
t1D
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3 t2 t4
12
CY2277A
Switching Waveforms (continued)
CPU-CPU Clock Skew
CLK
CLK t5
CPU-SDRAM Clock Skew
CPUCLK
SDRAM t7
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
CPU_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External)
[17, 18]
Notes: 17. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 18. CPU_STOP may be applied asynchronously. It is synchronized internally.
13
CY2277A
Switching Waveforms (continued)
PCI_STOP [19, 20]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
t11
t18
t19
t12
SCL
t12 t13 t16 t14 t17 t15 t20
Notes: 19. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 20. PCI_STOP may be applied asynchronously. It is synchronized internally.
14
CY2277A
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints can be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
15
CY2277A
Test Circuit
VDDQ3
48 3 0.1 F 46 7 0.1 F 10 43 40 37 15 0.1 F 34 17 31 28 0.1 F 25 0.1 F OUTPUTS CLOAD 0.1 F VDDCPU 0.1 F VDDQ2
0.1 F
0.1 F
21
24
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2277APAC-1 CY2277APVC-1 CY2277APAC-1M CY2277APVC-2 CY2277APVC-3 CY2277APAC-12 CY2277APVC-12 Document #: 38-00612-D Package Name Z48 O48 Z48 O48 O48 Z48 O48 Package Type 48-Pin TSSOP 48-Pin SSOP 49-Pin TSSOP 48-Pin SSOP 48-Pin SSOP 48-Pin TSSOP 48-Pin SSOP Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial
16
CY2277A
Package Diagrams
48-Lead Shrunk Small Outline Package O48
51-85061-B
48-Lead Thin Shrunk Small Outline Package Z48
51-85059-A
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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